In a fabrication of semiconductor devices, many FinFETs rely on a tall gate structure. Such a structure may allow for a reduction in horizontal resistance. However, a tall gate structure typically results in high parasitic capacitance, and may require complex or costly metal chamfering and self-aligned contact (SAC) processes.
A need therefore exists for methodologies for fabrication of semiconductor devices, particularly FinFETs, having a low gate horizontal resistance without use of a tall gate structure, and a resulting device.